maximum ipv4 bgp prefix length of /24 ?

Fri Sep 29 22:19:25 UTC 2023

>
> I'm less assuming it and more reading it from this SIGCOMM paper:
> https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf

Which doesn't cover the subject at hand. Owen is correct here.

The LU block has separate reduced latency RAM that holds the data it uses.
(The FIB). Other memory in the chip is used for the other non-lookup
functions.

On Fri, Sep 29, 2023 at 6:14 PM William Herrin <bill at herrin.us> wrote:

> On Fri, Sep 29, 2023 at 3:11 PM Owen DeLong <owen at delong.com> wrote:
> > You continue to assume that there is a fast SRAM cache. I’m not sure
> > that is true. I think that all of the FIB RAM on the line cards is fast
> SRAM
> > and no cache.
>
> Hi Owen,
>
> I'm less assuming it and more reading it from this SIGCOMM paper:
> https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf
>
> Regards,
> Bill Herrin
>
>
> --
> William Herrin
> bill at herrin.us
> https://bill.herrin.us/
>
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