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--></style></head><body lang=EN-US link=blue vlink="#954F72" style='word-wrap:break-word'><div class=WordSection1><p class=MsoNormal>Saku,</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I have forwarded your questions to Sharada.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>All,</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>For this week – at 11:00am PST, Thursday 08/11, we will be joined by Guy Caspary (co-founder of <span style='font-size:10.5pt;font-family:"Segoe UI",sans-serif;color:black;background:white'>Leaba Semiconductor (acquired by Cisco -> SiliconOne)</span><span style='font-size:10.5pt;font-family:"Segoe UI",sans-serif;background:white'><o:p></o:p></span></p><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Segoe UI",sans-serif;color:black;background:white'><a href="https://m.youtube.com/watch?v=GDthnCj31_Y">https://m.youtube.com/watch?v=GDthnCj31_Y</a></span><span style='font-size:10.5pt;font-family:"Segoe UI",sans-serif;background:white'><o:p></o:p></span></p><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Segoe UI",sans-serif;background:white'><o:p> </o:p></span></p><p class=MsoNormal>For the next week, I’m planning to get one of main architects of Broadcom DNX (Jericho/Qumran/Ramon).</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Cheers,<o:p></o:p></p><p class=MsoNormal>Jeff<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><div style='mso-element:para-border-div;border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal style='border:none;padding:0in'><b>From: </b><a href="mailto:saku@ytti.fi">Saku Ytti</a><br><b>Sent: </b>Friday, August 5, 2022 12:15 AM<br><b>To: </b><a href="mailto:jefftant.ietf@gmail.com">Jeff Tantsura</a><br><b>Cc: </b><a href="mailto:nanog@nanog.org">NANOG</a>; <a href="mailto:jdoyle@juniper.net">Jeff Doyle</a><br><b>Subject: </b>Re: 400G forwarding - how does it work?</p></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thank you for this.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I wish there would have been a deeper dive to the lookup side. My open questions</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>a) Trio model of packet stays in single PPE until done vs. FP model of</p><p class=MsoNormal>line-of-PPE (identical cores). I don't understand the advantages of</p><p class=MsoNormal>the FP model, the Trio model advantages are clear to me. Obviously the</p><p class=MsoNormal>FP model has to have some advantages, what are they?</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>b) What exactly are the gains of putting two trios on-package in</p><p class=MsoNormal>Trio6, there is no local-switching between WANs of trios in-package,</p><p class=MsoNormal>they are, as far as I can tell, ships in the night, packets between</p><p class=MsoNormal>trios go via fabric, as they would with separate Trios. I can</p><p class=MsoNormal>understand the benefit of putting trio and HBM2 on the same package,</p><p class=MsoNormal>to reduce distance so wattage goes down or frequency goes up.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>c) What evolution they are thinking for the shallow ingress buffers</p><p class=MsoNormal>for Trio6. The collateral damage potential is significant, because WAN</p><p class=MsoNormal>which asks most, gets most, instead each having their fair share, thus</p><p class=MsoNormal>potentially arbitrarily low rate WAN ingress might not get access to</p><p class=MsoNormal>ingress buffer causing drop. Would it be practical in terms of</p><p class=MsoNormal>wattage/area to add some sort of preQoS towards the shallow ingress</p><p class=MsoNormal>buffer, so each WAN ingress has a fair guaranteed-rate to shallow</p><p class=MsoNormal>buffers?</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>On Fri, 5 Aug 2022 at 02:18, Jeff Tantsura <jefftant.ietf@gmail.com> wrote:</p><p class=MsoNormal>><o:p> </o:p></p><p class=MsoNormal>> Apologies for garbage/HTMLed email, not sure what happened (thanks</p><p class=MsoNormal>> Brian F for letting me know).</p><p class=MsoNormal>> Anyway, the podcast with Juniper (mostly around Trio/Express) has been</p><p class=MsoNormal>> broadcasted today and is available at</p><p class=MsoNormal>> https://www.youtube.com/watch?v=1he8GjDBq9g</p><p class=MsoNormal>> Next in the pipeline are:</p><p class=MsoNormal>> Cisco SiliconOne</p><p class=MsoNormal>> Broadcom DNX (Jericho/Qumran/Ramon)</p><p class=MsoNormal>> For both - the guests are main architects of the silicon</p><p class=MsoNormal>><o:p> </o:p></p><p class=MsoNormal>> Enjoy</p><p class=MsoNormal>><o:p> </o:p></p><p class=MsoNormal>><o:p> </o:p></p><p class=MsoNormal>> On Wed, Aug 3, 2022 at 5:06 PM Jeff Tantsura <jefftant.ietf@gmail.com> wrote:</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Hey,</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > This is not an advertisement but an attempt to help folks to better understand networking HW.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Some of you might know (and love 😊) “between 0x2 nerds” podcast Jeff Doyle and I have been hosting for a couple of years.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Following up the discussion we have decided to dedicate a number of upcoming podcasts to networking HW, the topic where more information and better education is very much needed (no, you won’t have to sign NDA before joining 😊), we have lined up a number of great guests, people who design and build ASICs and can talk firsthand about evolution of networking HW, complexity of the process, differences between fixed and programmable pipelines, memories and databases. This Thursday (08/04) at 11:00PST we are joined by one and only Sharada Yeluri - Sr. Director ASIC at Juniper. Other vendors will be joining in the later episodes, usual rules apply – no marketing, no BS.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > More to come, stay tuned.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Live feed: https://lnkd.in/gk2x2ezZ</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Between 0x2 nerds playlist, videos will be published to: https://www.youtube.com/playlist?list=PLMYH1xDLIabuZCr1Yeoo39enogPA2yJB7</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Cheers,</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Jeff</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > From: James Bensley</p><p class=MsoNormal>> > Sent: Wednesday, July 27, 2022 12:53 PM</p><p class=MsoNormal>> > To: Lawrence Wobker; NANOG</p><p class=MsoNormal>> > Subject: Re: 400G forwarding - how does it work?</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > On Tue, 26 Jul 2022 at 21:39, Lawrence Wobker <ljwobker@gmail.com> wrote:</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > > So if this pipeline can do 1.25 billion PPS and I want to be able to forward 10BPPS, I can build a chip that has 8 of these pipelines and get my performance target that way. I could also build a "pipeline" that processes multiple packets per clock, if I have one that does 2 packets/clock then I only need 4 of said pipelines.. and so on and so forth.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Thanks for the response Lawrence.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > The Broadcom BCM16K KBP has a clock speed of 1.2Ghz, so I expect the</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > J2 to have something similar (as someone already mentioned, most chips</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > I've seen are in the 1-1.5Ghz range), so in this case "only" 2</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > pipelines would be needed to maintain the headline 2Bpps rate of the</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > J2, or even just 1 if they have managed to squeeze out two packets per</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > cycle through parallelisation within the pipeline.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal>> > Cheers,</p><p class=MsoNormal>> ></p><p class=MsoNormal>> > James.</p><p class=MsoNormal>> ></p><p class=MsoNormal>> ></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>-- </p><p class=MsoNormal> ++ytti</p><p class=MsoNormal><o:p> </o:p></p></div></body></html>