Clear Channel on a T1

Thu Mar 22 22:19:35 UTC 2001

>From: "Douglas A. Dever" <dever at hq.oh.verio.net>
>Reply-To: dever at verio.net
>To: CARL.P.HIRSCH at sargentlundy.com
>CC: nanog at merit.edu
>Subject: Re: Clear Channel on a T1
>Date: Thu, 22 Mar 2001 14:56:46 -0500 (EST)
>
>
>
>
>I'm quite suprised they'd offer you a data circuit that wasn't b8zs. I 
>think they're just using this as a way to get an extra couple of bucks per 
>month per circuit.  Without falling into a long discorse about timing on a 
>DS1, the bottom line is that you get ~1.54Mbit/sec because the data stream 
>is manipulated to maintain timing.  A non-clear channel data circuit would 
>only use 7 bits for data, with the 8th bit always being a 1 to maintain 
>timing.

Forcing the 8th bit to a '1' isn't done to maintain timing.

The 8th bit was forced to a '1' to maintain ones density on the T1 line.  
Early T1 specs did not allow more than 15 consecutive zeros to be 
transmitted because the T1 repeaters along the line rely on periodic pulses 
to keep their oscillators active. It was not a problem for voice circuits, 
since voice DS0s would contain a '1' for the signaling bit, but there is a 
potential for data DS0s to contain a long string of zeros, and several 
contiguous data DS0s could result in a long sequence of zeros (more than 
15).

In fact, older CSUs would inject a '1' if more than 15 consecutive zeros 
were sent, thus corrupting the bit stream.  For a voice DS0, it was probably 
not detected.  For a data DS0, it would result in a corrupted data frame.

Of course, in the "modern" world, with B8ZS line coding insuring that there 
will always be line transitions (to keep the T1 repeaters happy), a constant 
stream of zeros can be sent on the data channels, and the line coding will 
inject ones (and remove them at the other end) so forcing the 8th bit to a 
one is no longer needed.

-rb

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