T1 Circuit actual throughput 1290Kbps

prue at ISI.EDU prue at ISI.EDU
Thu Jul 9 20:32:19 UTC 1998


>It isn't D4 or ESF framing that causes a loss in usable bandwidth on a 
>T1, but AMI line coding.  As stated above, when using AMI line coding, 
>the T1 will not be provisioned for clear channel (64k) DS0s, but will be 
>provisioned for 56k DS0s, thus providing an aggregate bandwidth of 1344 
>kbps.  The least significant zero of each DS0 is forced to a 'one', thus 
>insuring correct ones density on the line.  The better solution is B8ZS 
>coding, which allows full use of each DS0's bandwidth.

>Inverting the data on the router won't give you back the "lost" 192 kbps 
>of bandwidth, since you're still limited to using 56kb/s of each DS0.

Sorry but you are wrong.  AMI has a ones density requirement which
causes CSU's to inject ones if the data that is presented it doesn't
have enough ones transitions.  Running HDLC data inverted can and does
cause enough transitions so that the CSU won't inject a one (injecting
an error in the data) to keep the phone company multiplexers happy.

Several early CSU's had various options to permit you to run at speeds 
above 1.344 Mb/s including a scrambling method (not fool proof), various
proprietary encoding methods, and the hdlc invert option.  In all cases
if the encoding method failed to provide one's density then the CSU 
circuitry would inject the required ones.  Note that the ones stuffing in 
every low order channel bit exceeds the ones density requirement of
AMI ciruits.  Most AMI circuits require no more than 15 zero bits in a row
and at least three one bits in every 24 bits.  I believe that there was 
the FCC part 68 rule and the 62411 rule if I remember it right.  They 
were slightly different.  Most early CSU manufacturers took the easy
implementation method of low order bit ones stuffing, but that was not
the only solution nore the most bandwidth efficient solution to assuring
ones density and data intetrity.

However if you are running on a channelized T1 circuit then you really
are limited to 56k X 24 or 1.344 Mb/s.  That is not related to D4 or AMI.
You would see that with an ESF circuit as well.  

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