T1 Circuit actual throughput 1290Kbps
Robert E. Seastrom
rs at bifrost.seastrom.com
Thu Jul 9 15:05:15 UTC 1998
From: "Robert E. Seastrom" <rs at bifrost.seastrom.com>
Precisely. The most likely explanation is that the T1 is actually D4
framed,
uh, my wrong... it's the AMI not the D4 that causes the big hit. of
course, as a matter of course, D4/AMI and ESF/B8ZS go together and you
never see combinations like D4/B8ZS... which, in answer to the fellow
who asked, is why you can't just invert the data on the HDLC and run
it down the line and get your 12% back... HDLC is layer 2, whilst
framing is layer 1...
---Rob
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