Film at 11:00

Sat Jan 4 09:51:10 UTC 1997

In cisco.external.nanog you write:

>not to make this too cisco specific, but...

>the number of entries in the forwarding cache on the
>sse is generally more than the number of routes in
>the bgp rib (because of the way the cache handles
>more-specifics of over-lapping aggregates).  so in
>addition to the raw number of routes in the rib, the
>efficiency (and scope) of aggregation are also
>important data points

>now a question.  what does an sse do when its cache
>fills?  it used to(*) bring down the whole sse, which
>doesn't really make much sense given that it's a
>cache and therefore it's normal operation for it to
>be incomplete.  anyone know an answer to that one?

SSE memory usage is monitored and if it falls below a particular
threshold, the ager will become more aggressive in aging entries..

--ravi

>/jws

>(*) -- "used to" implies that it happened before,
>which it did.  but that was largely due to the
>ineffeciency of the data structures, and the problem
>was solved such that 2 years (and counting) was added
>to its life

> > 
> >    Hmm, it's not news for us. 45K can hold core routing only as
> >    inter-back-bone router, not more.
> > 
> >    But why, why this crasy CISCO could not predict future when
> >    they designed 45K routers? It was not difficult  for them
> >    develop this box to cary 64 or 128MB RAM.
> > 
> >    >      Looks like the 45k mark was reached:
> >    >
> >    >   Folks with 7000's and SSE's should start monitoring their memory
> >    >   utilization via "show sse summary".
> > 
> > There's a couple of comments here:
> > 
> > First, 45k is not the limit.  More like 60k.  You'll pardon me for being
> > cautious. 
> > 
> > The limitation is not DRAM.  It's the 64k words of SRAM that the SSE uses
> > for its high speed forwarding table.  You don't want to pay for 64Mbytes of
> > SRAM.  ;-)
> > 
> > When cisco's engineers designed the SSE, we knew very well what was
> > happening.  We expected to be given the opportunity to produce subsequent
> > hardware which implemented the SSE in an ASIC.  If, by that time, CIDR
> > hadn't killed off the exponential growth, we would have expanded the
> > address space.  Unfortunately, cisco management decided that the SSE ASIC
> > should not be implemented (a mistake which, to my knowledge, cisco has not
> > corrected).  Thus, the 7500 exists without an SSE.
> > 
> > Tony