Film at 11:00
tli at jnx.com
Thu Jan 2 06:24:01 UTC 1997
There's not enough volume in high-end box market to get to the break-even
point on the price-performance.
That's not clear.
Providing that there's a way to get a bunch of cheapo CPUs to do the
True, but there's a complexity hit (which translates into a reliability hit
and a development lag) from this approach.
And don't forget the DRAM vs SRAM issue. I did the arithmetic.
Fortunately, there are new memory technologies today that are more
interesting than those when we started work on the SSE. And ASIC
technology helps you further here...
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